F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/27/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.15. PHY Reconfiguration Interface

Table 77.  PHY Reconfiguration Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
xcvr_reconfig_readdata[7:0] Output EP/RP/BP xcvr_reconfig_clk Avalon-MM read data outputs
xcvr_reconfig_readdatavalid Output EP/RP/BP xcvr_reconfig_clk Avalon-MM read data valid. When asserted, the data on xcvr_reconfig_readdata[7:0] is valid.
xcvr_reconfig_write Input EP/RP/BP xcvr_reconfig_clk Avalon-MM write enable
xcvr_reconfig_read Input EP/RP/BP xcvr_reconfig_clk Avalon-MM read enable
xcvr_reconfig_address[24:0] Input EP/RP/BP xcvr_reconfig_clk

Avalon-MM address bit[24:21] are used to indicate channel number.

xcvr_reconfig_writedata[7:0] Input EP/RP/BP xcvr_reconfig_clk Avalon-MM write data inputs
xcvr_reconfig_waitrequest Output EP/RP/BP xcvr_reconfig_clk When asserted, this signal indicates that the PHY is not ready to respond to a request.