F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/27/2023
Document Table of Contents

A. TPH Requester Enhanced Capability Header (Offset 0x0)

Table 130.  TPH Requester Enhanced Capability Header
Bits Register Description Default Value Access
[15:0] PCI Express Extended Capability ID 0x0017 RO
[19:16] Capability Version 0x1 RO
[31:20] Next Capability Pointer: Points to ATS Capability when present, NULL otherwise.

Programmed via Programming Interface.


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