4.2. TLP Bypass Mode
- The upstream port or the downstream port of a switch.
- A custom implementation of a Transaction Layer to meet specific user requirements.
|IP Mode||Port Mode|
The F-Tile Avalon-ST IP IP in TLP Bypass mode still includes some of the PCIe configuration space registers related to link operation.
F-Tile Avalon-ST IP interfaces with the application logic via the Avalon-ST interface (for all TLP traffic), the User Avalon-MM interface (via Hard IP Reconfiguration interface, for Lite TL’s configuration registers access) and other miscellaneous signals.
In TLP bypass mode, F-Tile supports the autonomous Hard IP feature. It responds to configuration accesses before the FPGA fabric enters user mode with Completions with a CRS code. However, in TLP bypass mode, CvP init and update are not supported.
When the TLP Bypass feature is enabled, the F-Tile Avalon-ST IP does not process received TLPs internally but outputs them to the user application. This allows the application to implement a custom Transaction Layer.
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