F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
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5.6. Hard IP Status Interface
This interface includes the signals that are useful for debugging, such as the link status signal, LTSSM state outputs, etc. These signals are available when the optional Power Management interface is enabled.
Signal Name | Direction | EP/RP/BP | Clock Domain | Description |
---|---|---|---|---|
p#_link_up_o | Output | EP/RP/BP | coreclkout_hip | When asserted, this signal indicates the link is up. |
p#_dl_up_o | Output | EP/RP/BP | coreclkout_hip | When asserted, this signal indicates the Data Link (DL) Layer is active. |
p#_ltssm_state_o | Output | EP/RP/BP | coreclkout_hip |
Indicates the LTSSM state:
|
p#_surprise_down_err_o | Output | EP/RP/BP | Async | Indicates that a surprise down event is occurring in the controller. |