F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 2/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.14. Hard IP Reconfiguration Interface

Table 76.  Hard IP Reconfiguration Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_hip_reconfig_readdata[7:0] Output EP/RP/BP p#_hip_reconfig_clk Avalon-MM read data outputs
p#_hip_reconfig_readdatavalid Output EP/RP/BP p#_hip_reconfig_clk Avalon-MM read data valid. When asserted, the data on hip_reconfig_readdata[7:0] is valid.
p#_hip_reconfig_write Input EP/RP/BP p#_hip_reconfig_clk Avalon-MM write enable
p#_hip_reconfig_read Input EP/RP/BP p#_hip_reconfig_clk Avalon-MM read enable
p#_hip_reconfig_address[20:0] Input EP/RP/BP p#_hip_reconfig_clk Avalon-MM address
p#_hip_reconfig_writedata[7:0] Input EP/RP/BP p#_hip_reconfig_clk Avalon-MM write data inputs
p#_hip_reconfig_waitrequest Output EP/RP/BP p#_hip_reconfig_clk When asserted, this signal indicates that the IP core is not ready to respond to a request.
dummy_user_avmm_rst Input EP/RP/BP N/A Dummy reset signal. You can tie it to ground or leave it floating when using Hard IP Reconfiguration Interface.