3.3.2. Avalon-ST RX
The Application Layer receives data from the Transaction Layer of the PCI Express IP core over the Avalon-ST RX interface. The application must assert rx_st_ready_i before transfers can begin. This interface supports two rx_st_sop_o signals and two rx_st_eop_o signals per cycle when the F-Tile IP is operating in a x16 configuration.
The x16 core provides two segments with each one having 256 bits of data (rx_st_data_o[511:256] and rx_st_data_o[255:0]), 128 bits of header (rx_st_hdr_o[255:128] and rx_st_hdr_o[127:0]), and 32 bits of TLP prefix (rx_st_tlp_prfx_o[63:32] and rx_st_tlp_prfx_o[31:0]). If this core is configured in the 1x16 mode, both segments are used, so the data bus becomes a 512-bit bus rx_st_data_o[511:0]. The start of packet can appear in the upper segment or lower segment, as indicated by the rx_st_sop_o[1:0] signals.
To achieve the expected performance in Gen4 x16 mode, the user application needs to take advantage of this segmented bus architecture. Otherwise, some performance reduction may occur.
If this core is configured in the 2x8 mode, only the lower segment is used. In this case, the data bus is a 256-bit bus rx_st_data_o[255:0]. Finally, if this core is configured in the 4x4 mode, only the lower segment is used and only the MSB 128 bits of data are valid. In this case, the data bus is a 128-bit bus rx_st_data_o[127:0].
The x8 core provides one segment with 256 bits of data, 128 bits of header and 32 bits of TLP prefix. If this core is configured in 4x4 mode, only the LSB 128 bits of data are used.
The x4 core provides one segment with 128 bits of data, 128 bits of header and 32 bits of TLP prefix.
RX Flow Control
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