F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 2/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.2. Generating Tile Files

The Support-Logic Generation is a pre-synthesis step used to generate tile-related files needed for simulation and hardware design. The tile files generation is a required step before simulation. You can run Analysis & Elaboration on the Processing menu in the Intel® Quartus® Prime Pro Edition software to generate the F-Tile specific tiles file for your design. The Support-Logic Generation command runs automatically as part of the process.

A successful tile file generation results in the <IP_instance_name>_auto_tiles.x files where x represents necessary file extensions. The generated files are located the support_logic folder under the project directory and contain the full netlist for simulation and synthesis.