SDI II Intel® FPGA IP User Guide

ID 683133
Date 12/09/2022
Public
Document Table of Contents

6.4. Transceiver Signals

Table 24.  Transceiver Serial Data Pins (for Arria V, Cyclone V, and Stratix V Devices)
Signal Direction Description
sdi_tx

Output

Transmitter serial out.

sdi_tx_b

Output

Transmitter serial out for link B.

Note: Applicable for HD-SDI dual link configuration only.
sdi_rx

Input

Receiver serial in.

sdi_rx_b

Input

Receiver serial in for link B.

Note: Applicable for HD-SDI dual link configuration only.
Table 25.  Transceiver Signals
Signal Width Clock Domain Direction Description
xcvr_refclk_sel

1

tx_coreclk

Input

Transceiver reference clock select signal that selects which clock to be used.

  • 0 = xcvr_refclk
  • 1 = xcvr_refclk_alt

Applicable only when you enable the Tx PLL Dynamic Switching option.

Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile devices.
tx_pll_locked

1

Output

PLL locked signal (TX PLL0) for the Native PHY IP core.

Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile devices.
tx_pll_locked_alt

1

Output

PLL locked signal (TX PLL1) for the Native PHY IP core.

Applicable only when you enable the Tx PLL Dynamic Switching option.

Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile devices.
reconfig_to_xcvr

70N

Input

Dynamic reconfiguration input for the Native PHY IP core, where N is the reconfiguration interface.

  • N = 1 for receiver
  • N = 2 for transmitter and bidirectional
Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile devices.
reconfig_to_xcvr_b

70N

Input

Dynamic reconfiguration input for the Native PHY IP core, where N is the reconfiguration interface.

  • N = 1 for receiver
  • N = 2 for transmitter and bidirectional
Note: For HD-SDI dual link configuration only. Not applicable for Intel® Agilex™ F-tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
reconfig_from_xcvr

46N

Output

Dynamic reconfiguration output for the Native PHY IP core, where N is the reconfiguration interface.

  • N = 1 for receiver
  • N = 2 for transmitter and bidirectional
Note: Not applicable for Intel® Agilex™ F-tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
reconfig_from_xcvr_b

46N

Output

Dynamic reconfiguration output for the Native PHY IP core, where N is the reconfiguration interface.

  • N = 1 for receiver
  • N = 2 for transmitter and bidirectional
Note: For HD-SDI dual link configuration only. Not applicable for Intel® Agilex™ F-tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_sdi_start_reconfig

1

rx_coreclk

Output

Request to start dynamic reconfiguration. This signal stays asserted until rx_sdi_reconfig_done indicates that the reconfiguration process is complete.

Note: Applicable for dual rate, triple-rate, and multi-rate modes only.
rx_sdi_reconfig_done

1

Input

Indicates that dynamic reconfiguration has completed.

This signal should connect to the reconfiguration status signal of the external transceiver reconfiguration management.
  • For Agilex F-tile, Arria V, Cyclone V, and Stratix V devices, assertion of this signal indicates to the receiver that the process is done.
  • For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices, deassertion of this signal indicates to the receiver that the process is done.
Note: Applicable for dual rate, triple-rate, and multi-rate modes only.
rx_ready

1

Input

Status signal from the transceiver reset controller to indicate when Rx PHY sequence is complete.

Note: Applicable only for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile devices.
gxb_ltr

1

rx_coreclk

Output

Control signal to the transceiver rx_set_locktoref input signal.

Assertion of this signal programs the Rx CDR to lock manually to reference mode.

Note: Applicable only for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile devices.
gxb_ltd

1

rx_coreclk

Output

Control signal to the transceiver rx_set_locktodata input signal.

Note: Applicable only for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile devices.
rx_ready_b 1 -

Input

Status signal from Transceiver Reset Controller to indicate when Rx PHY reset sequence is complete for link B

For HD-SDI dual link receiver protocol configuration only. (Not supported anymore on A10 from 16.1 onwards).
gxb_ltr_b 1 rx_coreclk

Output

Control signal to transceiver rx_set_locktoref input port. When asserted, programs the RX CDR to manual lock to reference mode.

For HD-SDI dual link receiver protocol configuration only. (Not supported anymore on A10 from 16.1 onwards).
gxb_ltd_b 1 rx_coreclk

Output

Control signal to transceiver rx_set_locktodata input port. When asserted, programs the RX CDR to manual lock to data mode.

For HD-SDI dual link receiver protocol configuration only. (Not supported anymore on A10 from 16.1 onwards).
rx_xcvr_reset_ack

1

-

Input

Status signal from transceiver indicating that the Rx transceiver is fully in reset

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