SDI II Intel® FPGA IP User Guide

ID 683133
Date 12/09/2022
Public
Document Table of Contents

7.3.3. SDI II Rx Register Summary

Table 54.  SDI II Rx Register Summary
Address Register Description
0x50 STATUS Read this register to retrieve the core status.
0x51 RESERVED Reserved
0x52 ACTIVE_SAMPLE_COUNT Read this register to retrieve the active sample count.
0x53 F0_ACTIVE_LINE_COUNT Read this register to retrieve the active line count of field 0.
0x54 F1_ACTIVE_LINE_COUNT Read this register to retrieve the active line count of field 1.
0x55 – 0x57 RESERVED Reserved.
0x58 VIDEO_MODE_STANDARD Read this register to retrieve the SDI mode and video standard.
0x59 – 0x5B RESERVED Reserved.
0x5C COLOR_PATTERN Read this register to retrieve the color pattern.
0x5D VPID_BYTE1 Read this register to retrieve the video payload ID byte 1.
0x5E VPID_BYTE2 Read this register to retrieve the video payload ID byte 2.
0x5F VPID_BYTE3 Read this register to retrieve the video payload ID byte 3.
0x60 VPID_BYTE4 Read this register to retrieve the video payload ID byte 4.
0x61 – 0x63 RESERVED Reserved
0x64 CONTROL Write to this register to control the core.

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