SDI II Intel® FPGA IP User Guide

ID 683133
Date 12/09/2022

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Document Table of Contents Dynamic Reconfiguration

To implement dynamic reconfiguration in F-tile devices, you need to use F-tile Dynamic Reconfiguration Suite IP in Intel® FPGA IP catalog. For more details on the IP, refer to F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide.

To work with this IP, create an F-tile PMA/FEC Direct PHY Multirate Intel® FPGA IP and a secondary profiles for each of the data rate you want to support. For instance, a triple-rate SDI which supports 3 different data rates – 270 Mbps (SD-SDI), 1.485 Gbps (HD-SDI) and 2.97 Gbps (3G-SDI), requires 1 PHY base profile and 2 secondary profiles with 3 different data rate configurations. However, since 3G-SDI and SD-SDI can share the same PHY configuration in SDI II Intel® FPGA IP’s transceiver handling, only 1 secondary profile has to be created in F-tile PMA/FEC Direct PHY Multirate Intel® FPGA IP on the RX side. For the TX side, the single rate version of F-tile PMA/FEC Direct PHY Intel® FPGA IP instance is used as the IP does not require reconfiguration between data rates, because the IP is doing oversampling. Refer to TX Sample topic for more information. However, if your design requires two reference clocks switching for NTSC and PAL rates, F-tile PMA/FEC Direct PHY Multirate Intel® FPGA IP is required to connect the TX PLL reference clock to another clock port.

At the F-tile PMA/FEC Direct PHY Multirate IP parameter editor, you should enable the following three parameters under the Datapath Avalon Memory-Mapped Interface:
  • Enable datapath Avalon interface
  • Enable soft CSR
  • Enable reconfiguration soft CSR
Figure 53. Datapath Avalon Memory-Mapped Interface Options

After instantiating these instances, which act as a profile instance, you must connect the reconfig_pdp clock (you can share the same clock as i_csr_clk port from the F-tile Dynamic Reconfiguration Suite Intel® FPGA IP) and reset ports, and terminate the Avalon® memory-mapped interface ports. You must include the following assignments in the project’s .qsf file to define the reconfiguration group.

set_instance_assignment -name IP_RECONFIG_GROUP <your base profile ID> -to <Multirate PHY base profile instance>

set_instance_assignment -name IP_COLOCATE F_TILE -from <Dynamic reconfig IP instance> -to <Multirate PHY base profile instance>

SDI II Intel® FPGA IP’s design example contains RTL modules of the reconfiguration controller, as well as an arbiter to interact between SDI II IP and the Dynamic Reconfiguration Suite IP. For more details on the RTL example, refer to F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide.