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Visible to Intel only — GUID: kpv1653978619541
Ixiasoft
Visible to Intel only — GUID: kpv1653978619541
Ixiasoft
7.3.2. SDI II Tx Register Description
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:1 | - | - | - |
Status | 0 | RO | When asserted, the SDI II Tx is producing data. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Video mode match | 31:0 | RO | Before any user specified mode is matched, this register reads back 0 indicating the default values are selected. Once a match has been made, the register reads back 0x1. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Video mode bank selected | 31:0 | RW | Writes to the video mode registers (0x54-0x6D) reflect to the video mode bank selected by this one-hot register. Only 1 mode bank is available. Writes 0x1 to this register to select mode bank 1. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:1 | - | - | - |
Interlaced | 0 | RW | Set to 1 for interlaced video. Set to 0 for progressive video. |
0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
Sample Count | 15:0 | RW | Specifies the active picture width of the field. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
F0 line count | 15:0 | RW | Specifies the active picture height of progressive video or interlaced video field 0. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
F1 line count | 15:0 | RW | Specifies the active picture height of interlaced video field 1. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
Horizontal blanking | 15:0 | RW | Specifies the length of the horizontal blanking length period in samples. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
Vertical blanking | 15:0 | RW | Specifies the length of the vertical blanking period in lines. For interlaced video, this is the vertical blanking period between the end of field 0 active picture and the start of field 1 active picture | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
F0 vertical blanking | 15:0 | RW | Specifies the length of the field 0 vertical blanking period (interlaced video only) in lines. This is the vertical blanking period between the end of field 1 active picture and the start of field 0 active picture. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
Active picture line | 15:0 | RW | Specifies the line number given to the first line of active picture. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
F0 vertical rising | 15:0 | RW | Specifies the line number given to the start of field 0’s vertical blanking (after the end of field 0 active picture). | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
Field rising | 15:0 | RW | Specifies the line number given to the end of field 0 and the start of field 1. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:16 | - | - | - |
Field falling | 15:0 | RW | Specifies the line number given to the end of field 1 and the start of field 0. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:4 | - | - | - |
SDI mode | 3 | RW | Specifies the SDI mode. 0x1: 2081-10-2018 6G-SDI Mode 2. 0x0: 2081-10-2018 6G-SDI Mode 1, 2082-10-2018 12G-SDI Mode 1. Writing to this register when SDI video standard is 3G-SDI, HD-SDI and SD-SDI has no effect. |
0x0 |
SDI video standard | 2:0 | RW | Specifies the SDI video standard. 0x0: SD-SDI 0x1: HD-SDI 0x2: 3G-SDI Level B 0x3: 3G-SDI Level A 0x4: 6G-SDI Level B 0x5: 6G-SDI Level A 0x7: 12G-SDI Level A |
0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:8 | - | - | - |
SDI video payload ID byte 1 | 7:0 | RW | Specifies the video payload byte 1 that to be inserted by the core. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:8 | - | - | - |
SDI video payload ID byte 2 | 7:0 | RW | Specifies the video payload byte 2 that to be inserted by the core. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:8 | - | - | - |
SDI video payload ID byte 3 | 7:0 | RW | Specifies the video payload byte 3 that to be inserted by the core. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:8 | - | - | - |
SDI video payload ID byte 4 | 7:0 | RW | Specifies the video payload byte 4 that to be inserted by the core. | 0x0 |
Name | Bit(s) | Access | Description | Reset |
---|---|---|---|---|
Reserved | 31:1 | - | - | - |
Video mode valid | 0 | WO | Set to 0 before programming the video mode registers (0x54 – 0x69). Set to 1 to indicate that the video mode registers (0x54 – 0x69) programmed are valid and can be used for video output. |
0x0 |