SDI II Intel® FPGA IP User Guide

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ID 683133
Date 12/09/2022
Public
Document Table of Contents
Document Table of Contents
1. SDI II IP Core Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough
3.2.1. Creating a New Intel® Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices 5.4.6. Intel FPGA Video Streaming Interface
5.4.6. Intel FPGA Video Streaming Interface
5.4.6.1. RGB Pixel Packing 5.4.6.2. YCbCr 444 Pixel Packing 5.4.6.3. YCbCr 422 Pixel Packing 5.4.6.4. Supported Modes
6. SDI II IP Core Signals
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals
6.2.1. Image Mapping
6.3. Receiver Protocol Signals
6.3.1. rx_format
7. SDI II IP Core Design Considerations
7.1. Transceiver Handling Guidelines 7.2. Timing Violation 7.3. SDI II IP Core Registers
7.1. Transceiver Handling Guidelines
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices 7.1.3. Handling Transceiver in Intel® Agilex™ F-tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
7.1.3. Handling Transceiver in Intel® Agilex™ F-tile Devices
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Transceiver Settings 7.1.3.3. TX Transceiver Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. Dynamic Reconfiguration 7.1.3.6. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.3. SDI II IP Core Registers
7.3.1. SDI II Tx Register Summary 7.3.2. SDI II Tx Register Description 7.3.3. SDI II Rx Register Summary 7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile Devices
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon-MM Translators
8.2.2. Design Reference
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design
8.2.3.1. Simulation Run Time
1. SDI II IP Core Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

7.3.2. SDI II Tx Register Description

Table 34.  STATUS (0x50)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Status 0 RO When asserted, the SDI II Tx is producing data. 0x0
Table 35.  VIDEO_MODE_MATCH (0x51)
Name Bit(s) Access Description Reset
Video mode match 31:0 RO Before any user specified mode is matched, this register reads back 0 indicating the default values are selected. Once a match has been made, the register reads back 0x1. 0x0
Table 36.  VIDEO_MODE_BANK_SELECT (0x53)
Name Bit(s) Access Description Reset
Video mode bank selected 31:0 RW Writes to the video mode registers (0x54-0x6D) reflect to the video mode bank selected by this one-hot register. Only 1 mode bank is available. Writes 0x1 to this register to select mode bank 1. 0x0
Table 37.  VIDEO_MODE_CONTROL (0x54)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Interlaced 0 RW

Set to 1 for interlaced video.

Set to 0 for progressive video.

0x0
Table 38.  VIDEO_MODE_SAMPLE_COUNT (0x55)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
Sample Count 15:0 RW Specifies the active picture width of the field. 0x0
Table 39.  VIDEO_MODE_F0_LINE_COUNT (0x56)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 line count 15:0 RW Specifies the active picture height of progressive video or interlaced video field 0. 0x0
Table 40.  VIDEO_MODE_F1_LINE_COUNT (0x57)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F1 line count 15:0 RW Specifies the active picture height of interlaced video field 1. 0x0
Table 41.  VIDEO_MODE_HORIZONTAL_BLANKING (0x5A)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
Horizontal blanking 15:0 RW Specifies the length of the horizontal blanking length period in samples. 0x0
Table 42.  VIDEO_MODE_VERTICAL_BLANKING (0x5D)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
Vertical blanking 15:0 RW Specifies the length of the vertical blanking period in lines. For interlaced video, this is the vertical blanking period between the end of field 0 active picture and the start of field 1 active picture 0x0
Table 43.  VIDEO_MODE_F0_VERTICAL_BLANKING (0x60)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 vertical blanking 15:0 RW Specifies the length of the field 0 vertical blanking period (interlaced video only) in lines. This is the vertical blanking period between the end of field 1 active picture and the start of field 0 active picture. 0x0
Table 44.  VIDEO_MODE_ACTIVE_PICTURE_LINE (0x61)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
Active picture line 15:0 RW Specifies the line number given to the first line of active picture. 0x0
Table 45.  VIDEO_MODE_F0_VERTICAL_RISING (0x62)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 vertical rising 15:0 RW Specifies the line number given to the start of field 0’s vertical blanking (after the end of field 0 active picture). 0x0
Table 46.  VIDEO_MODE_FIELD_RISING (0x63)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
Field rising 15:0 RW Specifies the line number given to the end of field 0 and the start of field 1. 0x0
Table 47.  VIDEO_MODE_FIELD_FALLING (0x64)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
Field falling 15:0 RW Specifies the line number given to the end of field 1 and the start of field 0. 0x0
Table 48.  VIDEO_MODE_STANDARD (0x65)
Name Bit(s) Access Description Reset
Reserved 31:4 - - -
SDI mode 3 RW Specifies the SDI mode.

0x1: 2081-10-2018 6G-SDI Mode 2.

0x0: 2081-10-2018 6G-SDI Mode 1,

2082-10-2018 12G-SDI Mode 1.

Writing to this register when SDI video standard is 3G-SDI, HD-SDI and SD-SDI has no effect. 		0x0
SDI video standard 2:0 RW Specifies the SDI video standard.

0x0: SD-SDI

0x1: HD-SDI

0x2: 3G-SDI Level B

0x3: 3G-SDI Level A

0x4: 6G-SDI Level B

0x5: 6G-SDI Level A

0x7: 12G-SDI Level A 		0x0
Table 49.  VIDEO_MODE_VPID_BYTE1 (0x66)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 1 7:0 RW Specifies the video payload byte 1 that to be inserted by the core. 0x0
Table 50.  VIDEO_MODE_VPID_BYTE2 (0x67)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 2 7:0 RW Specifies the video payload byte 2 that to be inserted by the core. 0x0
Table 51.  VIDEO_MODE_VPID_BYTE3 (0x68)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 3 7:0 RW Specifies the video payload byte 3 that to be inserted by the core. 0x0
Table 52.  VIDEO_MODE_VPID_BYTE4 (0x69)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 4 7:0 RW Specifies the video payload byte 4 that to be inserted by the core. 0x0
Table 53.  VIDEO_MODE_VALID (0x6D)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Video mode valid 0 WO

Set to 0 before programming the video mode registers (0x54 – 0x69).

Set to 1 to indicate that the video mode registers (0x54 – 0x69) programmed are valid and can be used for video output. 		0x0
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