SDI II Intel® FPGA IP User Guide

ID 683133
Date 12/09/2022

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5.3.19. Convert SD Bits

This submodule is enabled when you set the SD Interface Bit Width parameter option to 20. This submodule converts the SD parallel data in 20 bits back to 10 bits as per the requirement for further processing.

This submodule contains a clock enable generator to generate two data valid pulses at every 11th clock cycle of the tx_pclk domain. Each time the data valid signal is asserted, this block alternately transmits the lower 10 bits and upper 10 bits of the SD 20-bit interface data to the downstream logic.