SDI II Intel® FPGA IP User Guide

ID 683133
Date 12/09/2022

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5.3.20. Insert Sync Bits

Inserting sync bits prevents long runs of 0s.

Repeating patterns of 3FF or 000h for 6G-SDI and 12G-SDI video standards in the 10-bit parallel interface may result in a long run of zeros feeding the scrambling polynomial. A long run of zeros goes up to a length of 160 "1"s and 339 "0"s, which may cause the generation of the pothole pathological condition.

To prevent long runs, this feature modifies the 10-bit parallel interface data stream. It replaces the two LSBs of repeated 3FF or 000 code words with sync-bit values of 10b for 000h words and 01b for 3FFh words.

Figure 23. Sync Bits

However, to ensure the words are synchronized and aligned in the receiver, this feature retains one complete sequence of preambles (3FFh 000h 000h) without modification.

Figure 24. Sync Bits Insertion Process