Intel® FPGA SDK for OpenCL™ Pro Edition: Custom Platform Toolkit User Guide

ID 683085
Date 3/28/2022
Document Table of Contents OpenCL Kernel Clock Generator

The OpenCL™ Kernel Clock Generator is a Platform Designer component that generates a clock output and a clock 2x output for use by the OpenCL kernels. An Avalon®-MM agent interface allows reprogramming of the phase-locked loops (PLLs) and kernel clock status information.
Table 4.  Parameter Settings for the OpenCL Kernel Clock Generator Component
Parameter Description
REF_CLK_RATE Frequency of the reference clock that drives the kernel PLL (that is, pll_refclk).
KERNEL_TARGET_CLOCK_RATE Frequency that the Intel® Quartus® Prime Pro Edition software attempts to achieve during compilation.

Keep this parameter at its default setting.

Table 5.  Signals and Ports for the OpenCL Kernel Clock Generator Component
Signal or Port Description
kernel_pll_refclk The reference clock for the kernel PLL. The frequency of this clock must match the frequency you specify for the REF_CLK_RATE component parameter.
clk The clock used for the host control interface. The clock rate of clk can be slow.
reset The reset signal that resets the PLL and the control logic. Resetting the PLL disables the kernel clocks temporarily. Connect this reset signal to the power-on reset signal in your system.
ctrl The agent port used to connect to the OpenCL host interface and to adjust the frequency based on the OpenCL kernel.


The kernel clock and its 2x variant that runs on twice the speed. The kernel_clk2x signal is directly exported from this interface. Because kernel_clk has internal Platform Designer connections, export it using a clock source component. You can also use the clock source to export the kernel reset. In addition, clock all logic at the board Platform Designer system interface with kernel_clk, except for any I/O that you add.
kernel_pll_locked (Optional) If the PLL is locked onto the reference clock, the value of this signal is 1. The host interface manages this signal normally; however, this signal is made available in the board Platform Designer system.