Intel® FPGA SDK for OpenCL™ Pro Edition: Custom Platform Toolkit User Guide

ID 683085
Date 3/28/2022
Document Table of Contents

2.2.5. channels

The Intel® FPGA SDK for OpenCL™ Pro Edition supports data streaming directly between kernels and I/O via explicitly named channels. Include the channels element in the board_spec.xml file if your accelerator board provides channels for direct kernel-to-I/O accesses. For the channels element, you must identify all the channel interfaces, which are implemented using the Avalon®-ST specification. Specify each channel interface via the interface attribute. Refer to the interface section for the parameters you must specify for each interface. The channel interface only supports data, and valid and ready Avalon-ST signals. The I/O channel defaults to 8-bit symbols and big-endian ordering at the interface level.
Example XML code:
  <interface name="udp_0" port="udp0_out"  type="streamsource" width="256"
  <interface name="udp_0" port="udp0_in"  type="streamsink" width="256"
  <interface name="udp_0" port="udp1_out"  type="streamsource" width="256"
  <interface name="udp_0" port="udp1_in"  type="streamsink" width="256"