Intel® FPGA SDK for OpenCL™ Pro Edition: Custom Platform Toolkit User Guide

ID 683085
Date 3/28/2022
Public
Document Table of Contents

1.4.1.2. Establishing Guaranteed Timing Flow

Deliver a design partition for nonkernel logic that has a clean timing closure flow as part of your Custom Platform.
  1. Create a placed and routed design partition using the Intel® Quartus® Prime Pro Edition software. This is the design partition for nonkernel logic.
  2. Import the post-fit partition from 1 into the top-level design as part of the compilation flow.
  3. Run the INTELFPGAOCLSDKROOT/ip/board/bsp/adjust_plls.tcl script as a post-flow process, where INTELFPGAOCLSDKROOT points to the path of the Intel® FPGA SDK for OpenCL™ Pro Edition installation.
    The adjust_plls.tcl script determines the maximum kernel clock frequency and stores it in the pll_rom on-chip memory of the OpenCL Kernel Clock Generator component.

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