Intel® FPGA SDK for OpenCL™ Pro Edition: Custom Platform Toolkit User Guide

ID 683085
Date 3/28/2022
Document Table of Contents

2.1. The Board Platform Designer Subsystem

When designing your board hardware, you have the option to create a Platform Designer subsystem within the top-level Platform Designer system (board.qsys) that contains all nonkernel logic.
The board Platform Designer subsystem is the main design entry point for a new accelerator board. It is the location where the instantiations of the OpenCL™ host and global memory interfaces occur. Your board design must have a minimum of 128 kilobytes (KB) of external memory. Any Avalon® Memory-Mapped (Avalon-MM) agent interface (for example, a block RAM) can potentially be a memory interface.

The diagram below represents a board system implementation in more details:

Note: Blocks denoted with an asterisk (*) are blocks that you have to add to the board Platform Designer subsystem.

The OpenCL host communication interface and global memory interface are the main components of the board system. The memory-mapped device (MMD) layer communicates, over some medium, with the intellectual property (IP) core instantiated in this Platform Designer system.

For example, an MMD layer executes on a PCI Express® (PCIe®)-based host interface, and the host interface generates Avalon interface requests from an Intel® PCIe endpoint on the FPGA.

Within the board Platform Designer subsystem, you can also define the global memory system available to the OpenCL kernel. The global memory system may consist of different types of memory interfaces. Each memory type may consist of one, two, four, or eight banks of physical memory. All the banks of a given memory type must be the same size in bytes and have equivalent interfaces. If you have streaming I/O, you must also include the corresponding IP in the board Platform Designer system. In addition, you must update the board_spec.xml file to describe the channel interfaces.