Intel® FPGA SDK for OpenCL™ Pro Edition: Custom Platform Toolkit User Guide

ID 683085
Date 3/28/2022
Document Table of Contents Creating the Board Platform Designer System

When designing your board hardware, you have the option to create a Platform Designer subsystem within system.qsys that contains all the board logic. In addition to organizing your design code, having this subsystem allows you to create a Intel® Quartus® Prime partition that you can preserve. To create your board system in a Platform Designer subsystem, you may modify the board.qsys template in the Custom Platform Toolkit.

An implementation of a board Platform Designer subsystem might include the following components:

  • Proper reset sequencing
  • Intel® FPGA SDK for OpenCL™ Pro Edition-specific components
  • Host-to-FPGA communication IP
  • Memory IP used for SDK's global memory
  • Streaming channels to board-specific interfaces

Refer to The Board Platform Designer System section for more information.

You can refer to the templates of the following hardware design files in one of the reference platform BSPs available at the FPGA Software Download Center:

  • board.qsys
  • top.v
  • top.qpf
  • board_spec.xml

Refer to the template of the post_flow.tcl file in one of the BSPs available at FPGA Software Download Center. If you need help with downloading the BSP, refer to the Downloading the Intel FPGA SDK for OpenCL Pro Edition topic in Intel FPGA SDK for OpenCL Pro Edition: Getting Started Guide.

Note: Starting from the 20.3 release, support for Windows and Linux OpenCL BSPs is removed. Use version 20.2 or older OpenCL BSPs available at FPGA Software Download Center as a reference. If you want to migrate your OpenCL BSP to a newer version, follow the recommended steps provided in the Reference Platform Porting Guides available under Intel FPGA SDK for OpenCL documentation.

To create non-kernel logic, perform the following tasks in the board.qsys top-level Platform Designer system or in a board Platform Designer subsystem:

  1. In Platform Designer, add your host and memory IPs to the Platform Designer system, and establish all necessary connections and exports.
    Attention: You might need to acquire separate IP licenses. For a list of available licensed and unlicensed IP solutions, visit the All Intellectual Property page of the Intel® FPGA website. For more information about each IP, click the link in the Product Name column to navigate to the product page.
    1. Connect your host interface clock such that it drives por_reset_controller/clk. Your design's global reset and clock inputs are fed to a reset counter (por_reset_counter). This reset counter then synchronizes to the host interface clock in the Merlin Reset Controller (por_reset_controller).
      The por_reset_counter ACL SW Reset component implements the power-on reset. It resets all the device hardware by issuing a reset for a number of cycles after the FPGA completes its configuration.
    2. Modify the parameters of the pipe_stage_host_ctrl Avalon® Memory-Mapped (Avalon-MM) Pipeline Bridge component such that it can receive requests from your host IP. Connect your host interface's Avalon-MM host port to the s0 port of pipe_stage_host_ctrl. Connect the m0 port of pipe_stage_host_ctrl to all the peripherals that must communicate with your host interface, including the OpenCL Kernel Clock Generator and the OpenCL Kernel Interface components.
    3. Adjust the number of clock_cross_kernel_mem_<N> Avalon-MM Clock Crossing Bridge components to match the number of memory interfaces on your board. This component performs clock crossing between the kernel and memory interfaces. Modify the parameters of each component so that they are consistent with the parameters of the OpenCL Memory Bank Divider component and the interface attribute described in board_spec.xml. Connect the m0 host, clock, and reset ports of clock_cross_kernel_mem_<N> (that is, m0, m0_clk, and m0_reset, respectively) to your memory IP.
      Important: Connect m0_reset in such a way that assertion of kernel_reset from the OpenCL Memory Bank Divider component triggers this reset.
  2. Customize the SDK-specific Platform Designer (Standard) system components.
    1. In Platform Designer, click Tools > Options. In the Options dialog box, add INTELFPGAOCLSDKROOT/ip/board to the Qsys IP Search Path and then click Finish.
    2. Instantiate the OpenCL Kernel Clock Generator component. Specify the component parameters, and connect the signals and ports as outlined in the OpenCL Kernel Clock Generator section.
    3. Instantiate the OpenCL Kernel Interface component. Specify the component parameters, and connect the signals and ports as outlined in the OpenCL Kernel Interface section.
    4. For each global memory type, instantiate the OpenCL Memory Bank Divider component. Specify the component parameters, and connect the signals and ports as outlined in the OpenCL Memory Bank Divider section.
      Attention: Set the parameters such that the resulting bank hosts have the equivalent address bits and burst widths as those from the kernel, as defined in the interface attribute of the global_mem element in the board_spec.xml file. For each memory bank, Platform Designer generates a host that inherits the same characteristics as your specifications.
  3. If you choose to create a Platform Designer subsystem for the nonkernel logic, export any necessary I/Os to the top-level system.qsys Platform Designer system.
  4. Edit the top-level top.v file to instantiate system.qsys and connect any board-specific I/Os.
  5. Set up the top.qpf Intel® Quartus® Prime project with all the necessary settings for your board design.
  6. Modify the post_flow.tcl file to include the Tcl code that generates the fpga.bin file during Intel® Quartus® Prime compilation.
    The fpga.bin file is necessary for programming the board.
  7. Edit the board_spec.xml file to include board-specific descriptions.