Intel® FPGA SDK for OpenCL™ Pro Edition: Custom Platform Toolkit User Guide

ID 683085
Date 3/28/2022
Document Table of Contents

1.4.1. Designing the Board Hardware

To design an accelerator board for use with the Intel® FPGA SDK for OpenCL™ Pro Edition, you must create all the board and system components, and the files that describe your hardware design to the Intel® FPGA SDK for OpenCL™ Offline Compiler.

Each board variant in the Custom Platform consists of an Intel® Quartus® Prime project, and a board_spec.xml XML file that describes the system to the offline compiler. The board_spec.xml file describes the interfaces necessary to connect to the kernel. The offline compiler generates a custom circuit based on the data from the board_spec.xml file. Then it incorporates the OpenCL kernel into the Platform Designer system you create for all nonkernel logic.

You must preserve the design of all nonkernel logic. You can preserve your design in the Intel® Quartus® Prime Pro Edition software via one of the following methods:

  • Create a design partition containing all nonkernel logic under a single HDL hierarchy and then export the partition. For example, you may create and export a board.qsys Platform Designer subsystem (see figure below). The top-level system.qsys Platform Designer system can then instantiate this exported board Platform Designer subsystem.
  • Implement the Configuration via Protocol (CvP) configuration scheme, which preserves all logic outside a design partition. In this case, you only need to create a partition around the kernel logic. You may place all nonkernel logic into a single top-level Platform Designer system file (for example, system.qsys).

You must design all the components and the board_spec.xml file that describe the system to the SDK.

Figure 1. Example System Hierarchy with a Board Platform Designer Subsystem

For more information, refer to the System Design of Intel® Stratix® 10 Reference Platform in the Intel® FPGA SDK for OpenCL™ : Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide