Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 2/05/2024
Document Table of Contents

1.3.3. The Intel® Quartus® Prime Simulation Library

The Intel® Quartus® Prime software includes the Intel® Quartus® Prime simulation library. This library is comprised of Verilog HDL and VHDL files in the following directory:


This library includes simulation models for all low-level blocks that you instantiate in your design. The library includes the following different types of low level blocks:

Table 1.  Low Level Blocks in Simulation Library
Low-Level Blocks Description
Gate-Level Primitives Gate-level primitives include simple, non-parameterized modules, such as AND gates and flip-flops. altera_primitives.v and altera_primitives.vhd define the gate-level primitives. These primitives are only used in RTL designs. Post-synthesis and post-fit netlists do not include these primitives. Rather, these netlists include ATOMs.
Basic IP Function Blocks Previously known as "megafuctions," these are basic parameterized blocks for functions such as FIFOs and multipliers. Only RTL designs use these blocks. Post-synthesis and post-fit netlists do not include these blocks.
ATOMs Also known as WYSIWYGs, ATOMs are the lowest level primitives in an Intel® Quartus® Prime design. There are different ATOM primitives, all of them parameterized modules with varying complexity. They represent the hardware blocks on the FPGA. For example there are ATOM modules that represent the I/O pins and buffers, FPGA lookup tables, DSP blocks, RAM blocks, and periphery blocks, such as high speed transceivers and hardened Ethernet and PCIe blocks. You are not expected to instantiate ATOMs directly in your RTL. Rather, the ATOMs are instantiated in the RTL files that the Intel® Quartus® Prime software generates. Since the Intel® Quartus® Prime synthesis maps the design to ATOMs, the post-synthesis and post-fit netlists are netlists of ATOMs, known as ATOM netlists. The Fitter places and routes the ATOM netlist.
HDL Library Files You compile the HDL library files into fixed logical locations, as Compiling Files into Library Directories describes. You must not compile the libraries for Questa* Intel® FPGA Edition. Instead use the included precompiled libraries.