Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

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ID 683080
Date 2/05/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Intel FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* and VCS MX Support 4. Cadence Xcelium* Parallel Simulator Support 5. Aldec Active-HDL and Riviera-PRO Support A. Intel® Quartus® Prime Standard Edition User Guides
1. Intel FPGA Simulation Basics x
1.1. Intel FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Types 1.5. Supported Simulation Flows 1.6. Supported Hardware Description Languages 1.7. Supported Simulators 1.8. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.9. Intel FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Intel® Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. Intel FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Intel® Quartus® Prime Simulation Library x
1.3.3.1. The Intel® Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
1.8. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) x
1.8.1. Setting Up NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.8.2. Running RTL Simulation (NativeLink Flow) 1.8.3. Running Gate-Level Simulation (NativeLink Flow)
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. QuestaSim* Simulation Setup Script Example 2.4. Sourcing QuestaSim* Simulator Setup Scripts 2.5. Unsupported Features 2.6. Siemens EDA QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
2.2.3. Generating Signal Activity Data for Power Analysis x
2.2.3.1. Generating Standard Delay Output for Power Analysis
3. Synopsys VCS* and VCS MX Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS and VCS MX Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
3.2. VCS and VCS MX Guidelines x
3.2.1. Simulating Transport Delays 3.2.2. Disabling Timing Violation on Registers 3.2.3. Generating Power Analysis Files
4. Cadence Xcelium* Parallel Simulator Support x
4.1. Generating Simulator Setup Script Templates 4.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 4.3. Cadence Xcelium* Parallel Simulator Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5.2. Aldec Active-HDL and Riviera-PRO Guidelines x
5.2.1. Compiling SystemVerilog Files 5.2.2. Disabling Timing Violation on Registers
Answers to Top FAQs
1. Intel FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Cadence Xcelium* Parallel Simulator Support
5. Aldec Active-HDL and Riviera-PRO Support
A. Intel® Quartus® Prime Standard Edition User Guides

5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts

Follow these steps to incorporate the generated ActiveHDL* or Riviera Pro* simulation scripts into a top-level project simulation script.
  1. The generated simulation script contains the following template lines. Cut and paste these lines into a new file. For example, sim_top.tcl. 
    # # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog -sv2k5 <your compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
  2. Delete the first two characters of each line (comment and space): 
     # TOP-LEVEL TEMPLATE - BEGIN
 #
 # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
 # construct paths to the files required to simulate the IP in your Quartus
 # project. By default, the IP script assumes that you are launching the
 # simulator from the IP script location. If launching from another
 # location, set QSYS_SIMDIR to the output directory you specified when you
 # generated the IP script, relative to the directory from which you launch
 # the simulator.
 #
 set QSYS_SIMDIR <script generation output directory>
 #
 # Source the generated IP simulation script.
 source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
 #
 # Set any compilation options you require (this is unusual).
 set USER_DEFINED_COMPILE_OPTIONS <compilation options>
 set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
 set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
 #
 # Call command to compile the Quartus EDA simulation library.
 dev_com
 #
 # Call command to compile the Quartus-generated IP simulation files.
 com
 #
 # Add commands to compile all design files and testbench files, including
 # the top level. (These are all the files required for simulation other
 # than the files compiled by the Quartus-generated IP simulation script)
 #
 vlog -sv2k5 <your compilation options> <design and testbench files>
 #
 # Set the top-level simulation or testbench module/entity name, which is
 # used by the elab command to elaborate the top level.
 #
 set TOP_LEVEL_NAME <simulation top>
 #
 # Set any elaboration options you require.
 set USER_DEFINED_ELAB_OPTIONS <elaboration options>
 #
 # Call command to elaborate your design and testbench.
 elab
 #
 # Run the simulation.
 run
 #
 # Report success to the shell.
 exit -code 0
 #
 # TOP-LEVEL TEMPLATE - END
  3. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  4. Refer to the following sim_top.tcl example content, where this file is in the same aldec/ sub-folder as the rivierapro_setup.tcl file. 
    # TOP-LEVEL TEMPLATE - BEGIN
#
# QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# construct paths to the files required to simulate the IP in your Quartus
# project. By default, the IP script assumes that you are launching the
# simulator from the IP script location. If launching from another
# location, set QSYS_SIMDIR to the output directory you specified when you
# generated the IP script, relative to the directory from which you launch
# the simulator.
#
set QSYS_SIMDIR ../
#
# Source the generated IP simulation script.
 source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
 #
 # Set any compilation options you require (this is unusual).
set USER_DEFINED_COMPILE_OPTIONS "" 
set USER_DEFINED_VHDL_COMPILE_OPTIONS "" 
set USER_DEFINED_VERILOG_COMPILE_OPTIONS "" 
#
 # Call command to compile the Quartus EDA simulation library.
dev_com
 #
 # Call command to compile the Quartus-generated IP simulation files.
com
 #
 # Add commands to compile all design files and testbench files, including
 # the top level. (These are all the files required for simulation other
 # than the files compiled by the Quartus-generated IP simulation script)
 #
vlog -sv2k5 $QSYS_SIMDIR/PLL_RAM.v
vlog -sv2k5 $QSYS_SIMDIR/testbench_1.v
 #
 # Set the top-level simulation or testbench module/entity name, which is
 # used by the elab command to elaborate the top level.
 #
set TOP_LEVEL_NAME tb
 #
 # Set any elaboration options you require.
 set USER_DEFINED_ELAB_OPTIONS "" 
 #
 # Call command to elaborate your design and testbench.
 elab
 #
 # Run the simulation.
run -all
 #
 # Report success to the shell.
 exit -code 0
 #
 # TOP-LEVEL TEMPLATE - END
  5. To view all available options, invoke the Active-HDL or Riviera-PRO license and launch the simulator by typing vsim in command-line mode. After the simulator launches, type help in the simulator Console panel. To view options related to a specific command, for example the vsim simulation command, type help vsim in the simulator Console panel.
  6. Run the new top-level script from the generated simulation directory in command-line mode. To run the simulation in GUI mode, type the following: 
    vsim -gui -l log.txt +access +r -lib dsn tb -do sim_top.tcl

    To run the simulation in command-line mode, type the following:

    vsim –c –do sim_top.tcl
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