Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 2/05/2024
Document Table of Contents Elaboration Options

There are many simulator specific elaboration options that you can specify. One common elaboration option preserves specific signal names so that their waveforms (a record of how the signals change with time) can be recorded during simulation. The rationale behind this option is explained below.

The elaboration stage generally includes an optimization step. The optimization step attempts to build an optimized executable simulation model that can run faster or consume less memory during simulation.

There are many signals (defined as wire, reg, or logic variables) in a typical design and testbench hierarchy. At the end of a simulation, any signal can produce a simulation waveform.

The optimization step may be unable to fully optimize the executable simulation model if most of the signals in the testbench hierarchy are preserved. Therefore, it is best to limit the signals that you preserve to those that require waveforms during simulation. You can specify the signals to preserve at varying level of granularity. For example, you can specify specific signal names, or all signals within a module instance.