Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 2/05/2024
Document Table of Contents

1.1. Intel FPGA Simulation Essential Elements

The following describes the essential elements required for Intel FPGA design simulation.


An Intel® Quartus® Prime design typically consists of a top-level design module containing a hierarchy of module instances, defined in one or more HDL files. The design that you intend to simulate is known as the Design Under Test (DUT).


To simulate the DUT (that is, a design), you must also provide a separate HDL module (referred to as the testbench module) that instantiates the DUT and additional logic to stimulate the DUT and to capture the output from the DUT. The testbench module can include a hierarchy of module instances related to the testbench, but that are not part of the design. You define the testbench modules in one or more HDL files.

Top-Level Testbench

A top level testbench module is the testbench module that instantiates all other design and testbench related modules. This is the module you simulate.

HDL Design and Testbench Files

Simulating a design requires HDL design files, and one or more HDL testbench files. Intel® Quartus® Prime designs typically consist of several modules that you define in multiple HDL files. These files can include HDL files generated by Intel® Quartus® Prime tool, such as Intel® Quartus® Prime Platform Designer.

Some of the modules instantiated in the design may be common to many designs. Examples of some common modules are low-level primitives, like AND and OR gates, and more complex blocks, such as multipliers and FIFOs.

The low level modules common to many designs are known as simulation library modules, and the files defining those modules are known as simulation library files. The Intel® Quartus® Prime software installation provides various simulation library files, as The Intel Quartus Prime Simulation Library describes.

The combination of design and testbench files includes all the modules that are instantiated in the top-level testbench module hierarchy, including all of the modules for the design, because the design is instantiated within the testbench hierarchy.

Executable Simulation Model

In order to simulate a design you must first generate an executable simulation model of the top-level testbench by running a set of simulator specific commands. You must then run the executable model to perform simulation. Running the executable model may require simulator specific commands. The executable model is typically a set of binary files specific to a simulator.

Simulator Commands

You must run one or more simulator commands to generate the executable simulation model and then to run the executable simulation model. The commands require the following inputs to generate an executable model of the top-level testbench module that you can simulate, as the Inputs and Commands to Generate and Run the Executable Model figure shows:

  • The name of the top-level testbench module.
  • The HDL design files, including files generated by tools such as Platform Designer, simulation library files, and testbench files.
Figure 1. Inputs and Commands to Generate and Run the Executable Simulation Model

Since you must run several commands to create and run the executable model to perform simulation, you can place the calls to the commands into one or more simulation scripts for convenience. These scripts can be Linux shell scripts, Tcl scripts, Perl, or Python scripts.