DisplayPort Arria® 10 FPGA IP Design Example User Guide

ID 683050
Date 4/29/2024
Document Table of Contents

2.8. Hardware Setup

The DisplayPort Intel® FPGA IP design example is 8Kp30 capable and performs a loop-through for a standard DisplayPort video stream.
  1. To run the hardware test, connect a DisplayPort-enabled source device to the DisplayPort FMC daughter card sink input.
  2. The DisplayPort sink decodes the port into a standard video stream and sends it to the clock recovery core.
  3. The clock recovery core synthesizes the original video pixel clock to be transmitted together with the received video data.
    Note: You require the clock recovery feature to produce video without using a frame buffer.
  4. The clock recovery core then sends the video data to the DisplayPort source and the Transceiver Native PHY TX block.
  5. Connect the DisplayPort FMC daughter card source port to a monitor to display the image.
Table 20.  On-board User LED Functions
LEDs Function

This LED indicates that the source is successfully lane-trained.

At this point, the IP core asserts rx0_vid_locked.


These LEDs illuminate design example lane counts.

  • 4'b0001 = 1 lane
  • 4'b0010 = 2 lanes
  • 4'b0100 = 4 lanes
USER_LED[7:6] These LEDs indicate the RX link rate.
  • 2'b00 = RBR
  • 2'b01 = HBR
  • 2'b10 = HBR2
  • 2'b11 = HBR3