DisplayPort Arria® 10 FPGA IP Design Example User Guide

ID 683050
Date 4/29/2024
Document Table of Contents

3.4.2. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in the Quartus® Prime Pro Edition software to generate the design example.
Before you begin, ensure to install the HDCP feature in the Quartus® Prime Pro Edition software.
  1. Click Tools > IP Catalog, and select Arria® 10 as the target device family.
    Note: The HDCP design example supports Stratix® 10, Arria® 10, and Agilex™ 7 devices.
  2. In the IP Catalog, locate and double-click DisplayPort Intel® FPGA IP . The New IP variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys.
  4. You may select a specific device in the Device field, or keep the default software device selection.
  5. Click OK. The parameter editor appears.
  6. Configure the desired parameters for both TX and RX
    Note: To enable the HDCP feature on RX, turn on the Enable GPU Mode parameter.
  7. Turn on Support HDCP Key Management parameter if you want to store the HDCP production key in an encrypted format in the external flash memory or EEPROM. Otherwise, turn off this parameter to store the HDCP production key in plain format in the FPGA.
  8. On the Design Example tab, select DisplayPort SST Parallel Loopback With PCR .
  9. Select Synthesis to generate the hardware design example.
  10. For Target Development Kit, select Arria 10 GX FPGA Development Kit . This causes the target device selected in step 4 to change to match the device on the development kit. For Arria 10 GX FPGA Development Kit, the default device is 10AX115S2F45I1SG.
  11. Click Generate Example Design to generate the project files and the software Executable and Linking Format (ELF) programming file.