DisplayPort Arria® 10 FPGA IP Design Example User Guide

ID 683050
Date 4/29/2024
Document Table of Contents

2.4.1. Arria® 10 DisplayPort SST TX-only Design Features

The TX-only design example demonstrates the transmission of a single video stream with a fixed pattern resolution (1920x1080 60Hz) using the Test Pattern Generator II.
Figure 9.  Arria® 10 DisplayPort TX-only Design
  • To generate TX-only design, turn on DisplayPort source's parameter, TX_SUPPORT_DP, and turn off DisplayPort sink's parameter, RX_SUPPORT_DP.
  • In this variant, the DisplayPort source's parameter, TX_SUPPORT_IM_ENABLE, is turned off and the standard VSYNC/HSYNC/DE video interface is used.
  • Test Pattern Generator II (TPG II) and Clocked Video Output II (CVO II) are integrated as video source to display 1080p60 color bar image.
  • The IOPLL drives the video clock at a 160 MHz to CVO II and 37.125 MHz (4 pixel per clock) to TPG II.
Note: Update the Test Pattern Generator II to lower resolution if the existing Resolution does not fit in to the configured Max Link Rate and Max Lane Count.