DisplayPort Arria® 10 FPGA IP Design Example User Guide

ID 683050
Date 4/29/2024
Document Table of Contents

2.4.2. Arria® 10 DisplayPort SST RX-only Design Features

The RX-only design example demonstrates the transmission of a single video stream from DisplayPort sink with Pixel Clock Recovery (PCR).
Figure 10.  Arria® 10 DisplayPort RX-only Design
  • To generate RX-only design, turn on DisplayPort sink's parameter, RX_SUPPORT_DP and turn off DisplayPort source's parameter, TX_SUPPORT_DP
  • In this variant, the DisplayPort source's parameter TX_SUPPORT_IM_ENABLE, is turned off and the standard VSYNCH/HSYNCH/DE video interface is used.
  • The IOPLL drives video clock at a fixed frequency of 160 MHz.
  • The DisplayPort sink receives video from external video source such as GPU and decodes it into parallel video interface.
  • The design uses the Pixel Clock Recovery (PCR) to recover the pixel clock according to the received MSA information from the sink and converts the RX parallel video interface to the standard VSYNCH/HSYNCH/DE interface.