DisplayPort Arria® 10 FPGA IP Design Example User Guide

ID 683050
Date 4/29/2024
Document Table of Contents

1.3. Generating the DisplayPort Intel® FPGA IP Design Example

Use the parameter editor in the Quartus® Prime software to generate the design example.
Note: You need a Nios® V evaluation license. Refer to the Nios® V Processor Licensing topic in the Nios® V Embedded Processor Design Handbook.
Figure 3. Generating the Design Flow
  1. Open Quartus® Prime.
  2. Click Tools > IP Catalog, and select Arria® 10 as the target device family.
    Note: The design example only support Arria® 10 devices.
  3. In the IP Catalog, locate and double-click DisplayPort Intel® FPGA IP . The New IP Variation window appears.
  4. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named or <your_ip>.qsys .
  5. Select an Arria® 10 device in the Device field, or keep the default Quartus® Prime software device selection.
  6. Click OK. The parameter editor appears.
  7. Configure the desired parameters for both TX and RX.
    Note: The DisplayPort design example generation flow supports only SST. Selecting the Support MST parameter prevents you from generating the example design.
    Note: The Nios® V software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios® V terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
  8. On the Design Example tab, select, DisplayPort SST TX-only, DisplayPort SST RX-only DisplayPort SST Parallel Loopback With PCR, or DisplayPort SST Parallel Loopback Without PCR.
  9. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
    Note: DisplayPort MST design examples are supported only in synthesis; they are not supported in simulation.
    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  10. For Target Development Kit, select Arria 10 GX FPGA Development Kit . If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit. For Arria 10 GX FPGA Development Kit, the default device is 10AX115S2F45I1SG .
  11. For FMC Revision, select the revision corresponding to the Bitec DisplayPort FMC daughter card present in your system. The different versions are not compatible with each other. It is important that the correct version is selected when the example design is generated:
  12. Click Generate Example Design to generate the project files and the software Executable and Linking Format (ELF) programming file.