DisplayPort Arria® 10 FPGA IP Design Example User Guide
ID
683050
Date
4/29/2024
Public
2.1. Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
4. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives
For the latest and previous versions of this user guide, refer to DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide. If an IP or software version is not listed, the user guide for the previous IP or software version applies.
IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.