Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example User Guide
ID
683026
Date
1/23/2025
Public
1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example User Guide
7. Interface Signals Description
Use the following tables to find the description of the signals in the design example. The pinout diagram for each design example specifies the width of the signals.