Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/08/2024
Document Table of Contents

2. 10GBASE-R Ethernet Design Example

The 10GBASE-R Ethernet design example demonstrates an Ethernet solution for Intel® Stratix® 10 devices using the LL 10GbE MAC Intel® FPGA IP, the native PHY IP, and a small form factor pluggable (SFP+) module.

Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor.