Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/23/2025
Public
Document Table of Contents

3.5. Hardware Testing

Follow the procedure to test the design example in the selected hardware.
In the Clock Controller application, which is part of the development kit, set the following frequencies:
  • U5, Out 0—125 MHz
  • U5, Out 5—644.53125MHz
  • U6, Out 8—125MHz