Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/08/2024
Document Table of Contents

5.3. Functional Description

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.

Figure 27. Block Diagram—1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature