Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/08/2024
Document Table of Contents

2.3.1. Design Components

Table 4.  Design Components
Component Description

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 10G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable 10GBASE-R register mode: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • TX and RX datapath Reset/Default To Enable: Selected
  • Use legacy XGMII Interface: Selected.
  • Use legacy Avalon Memory-Mapped Interface: Not Selected
  • Use legacy Avalon Streaming Interface: Not selected
  • The L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP configured for the 10GBASE-R protocol.
  • The preset sets the PHY's TX FIFO MODE to Phase Compensation and RX FIFO MODE to 10GBASE-R.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP. Resets the transceiver.
Address decoder Decodes the addresses of the components.
Reset synchronizer Synchronizes the reset of all design components.

Generates a TX serial clock for the Intel® Stratix® 10 10G transceiver.

  • Avalon® streaming single-clock and dual-clock FIFO.
  • Buffers the RX and TX data between the MAC IP and the client.

By default, the maximum packet length is supported up to 8000 bytes. You can configure the FIFO depth to increase the packet length. Refer to Configuring FIFO Depth for Streaming Loopback for steps to configure the FIFO depth.

Core fPLL Generates 312.5 MHz and 156.25 MHz clocks to the MAC IP, reset synchronizer, Ethernet traffic controller, address decoder, and FIFO.