Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/23/2025
Public
Document Table of Contents

3.2. Hardware and Software Requirements

Altera uses the following hardware and software to test the design example in a Linux system:

  • Quartus® Prime Pro Edition software
  • ModelSim* - Intel® FPGA Edition, ModelSim* -SE, VCS, and Xcelium* simulators
    Note: Altera does not recommend using ModelSim* -AE due to long simulation time.
  • For hardware testing:
    • Stratix® 10 GX Signal Integrity H-Tile (Production) Development Kit (1SG280HU1F50E2VG)
    • Cables—Insert QSFP28 loopback module in QSFP28 IF1 slot.