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1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example User Guide
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3.2. Hardware and Software Requirements
Altera uses the following hardware and software to test the design example in a Linux system:
- Quartus® Prime Pro Edition software
- ModelSim* - Intel® FPGA Edition, ModelSim* -SE, VCS, and Xcelium* simulators
Note: Altera does not recommend using ModelSim* -AE due to long simulation time.
- For hardware testing:
- Stratix® 10 GX Signal Integrity H-Tile (Production) Development Kit (1SG280HU1F50E2VG)
- Cables—Insert QSFP28 loopback module in QSFP28 IF1 slot.
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