Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/23/2025
Public
Document Table of Contents

7.4. PHY Interface Signals

Table 22.  PHY Interface Signals
Signal Direction Width Description

rx_serial_data

In

2

RX serial input data

tx_serial_data

Out

2

TX serial output data