Agilex™ 7 FPGA F-Series Development Kit User Guide

Download PDF
ID 683024
Date 11/12/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The QSFPDD Tab 4.2.5. The DDR4-0 Tab 4.2.6. The DDR4-2 Tab 4.2.7. The DDR4-3 Tab
5. Development Kit Hardware and Configuration x
5.1. Configure the FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device by AS Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID Settings in the Quartus® PrimeQSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Agilex™ 7 FPGA A.2. Configuration Support A.3. Clocks A.4. Memory Interfaces A.5. Transceiver Interfaces A.6. HPS Interface A.7. General Input and Output A.8. Power
A.2. Configuration Support x
A.2.1. JTAG Chain and Header A.2.2. Onboard Intel® FPGA Download Cable II
A.7. General Input and Output x
A.7.1. Switches A.7.2. Buttons A.7.3. LEDs
A.8. Power x
A.8.1. Power Sequence A.8.2. Power Measurement A.8.3. Temperature Monitor
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.2.1. JTAG Chain and Header

The following figure shows the JTAG chain connections. An option to bypass the Agilex™ 7 FPGA during board bring up is provided but not shown in the figure.
Figure 19. JTAG Chain on the Development Kit

The JTAG chain allows programming of the Agilex™ 7 FPGA and the MAX® 10 CPLD devices using the external Intel® FPGA Download Cable II dongle. The dongle can be used to program both the Agilex™ 7 FPGA and MAX® 10 CPLD via the external 2x5 pin 0.1" programming header. This header uses a shrouded vertical connector and is designed to be accessible from the PCIe* bracket side. This avoids having to remove the PC case to program the device when the board is installed in a closed system.

Level Two Title