Agilex™ 7 FPGA F-Series Development Kit User Guide

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ID 683024
Date 11/12/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The QSFPDD Tab 4.2.5. The DDR4-0 Tab 4.2.6. The DDR4-2 Tab 4.2.7. The DDR4-3 Tab
5. Development Kit Hardware and Configuration x
5.1. Configure the FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device by AS Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID Settings in the Quartus® PrimeQSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Agilex™ 7 FPGA A.2. Configuration Support A.3. Clocks A.4. Memory Interfaces A.5. Transceiver Interfaces A.6. HPS Interface A.7. General Input and Output A.8. Power
A.2. Configuration Support x
A.2.1. JTAG Chain and Header A.2.2. Onboard Intel® FPGA Download Cable II
A.7. General Input and Output x
A.7.1. Switches A.7.2. Buttons A.7.3. LEDs
A.8. Power x
A.8.1. Power Sequence A.8.2. Power Measurement A.8.3. Temperature Monitor
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

3.1. Default Settings

The Agilex™ 7 FPGA F-Series Development Kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the factory default switch settings table given below to return the board to its factory settings before proceeding forward.

Note: "X" refers to Don't Care in the table below.
Table 4.  Factory Default Switch Settings
Switch Default Position Function
SW1[1:3] OFF/ON/ON

Configuration mode setting bits.

By default, AS -> FAST mode
SW2[1:4] OFF/OFF/OFF/OFF
  • Selects the resource of the system MAX® 10 JTAG from USB PHY.
  • Enables Si5341’s outputs
  • Powers up Si52202
  • Enables UART interface
SW3[1:4] OFF/OFF/OFF/OFF

Enables all the I2C level shifter.
SW4[1:4] OFF/ON/ON/OFF
  • Selects the onboard Intel® FPGA Download Cable as JTAG master when external JTAG header is absent.
  • Bypass PWR MAX® 10 in JTAG chain.
  • Bypasses the FPGA HPS in JTAG chain.
  • Enables FPGA in JTAG chain.
SW5 SW5.5 to SW5.6

Powers off the board.
SW6[1:4] ON/OFF/OFF/OFF

PCIe* x16 mode is selected.
SW7.1 ON

Selects local clock as PCIe* reference clock.
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