Intel Agilex® 7 FPGA F-Series Development Kit User Guide

ID 683024
Date 1/18/2024
Public
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4.2.5. The DDR4-0 Tab

This tab allows you to read and write DDR4-0 memory on your board.

Figure 12. The DDR4-0 Tab

The following sections describe controls on this tab.

Start

Initiates DDR4 memory transaction performance analysis.

Stop

Terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:
  • Write, Read and Total performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
  • Write (MBps), Read (MBps) and Total (MBps): Show the number of bytes analyzed per second.
  • Data Bus: 72 bits (8 bits ECC) wide, reference clock is 33.33 MHz and the frequency is 1066 MHz double data rate 2133 MT/s.

Error Control

This control displays data errors detected during analysis and allows you to insert errors:
  • Detected Errors: Displays the number of data errors detected in the hardware.
  • Inserted Errors: Displays the number of errors inserted into the transaction stream.
  • Insert: Inserts a one-word error into the transaction stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
  • Clear: Resets the detected error and inserted error counters to zeroes.

Number of Addresses to Read and Write

Determines the number of addresses to use in each iteration of reads and writes.