Agilex™ 7 FPGA F-Series Development Kit User Guide

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ID 683024
Date 11/12/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The QSFPDD Tab 4.2.5. The DDR4-0 Tab 4.2.6. The DDR4-2 Tab 4.2.7. The DDR4-3 Tab
5. Development Kit Hardware and Configuration x
5.1. Configure the FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device by AS Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID Settings in the Quartus® PrimeQSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Agilex™ 7 FPGA A.2. Configuration Support A.3. Clocks A.4. Memory Interfaces A.5. Transceiver Interfaces A.6. HPS Interface A.7. General Input and Output A.8. Power
A.2. Configuration Support x
A.2.1. JTAG Chain and Header A.2.2. Onboard Intel® FPGA Download Cable II
A.7. General Input and Output x
A.7.1. Switches A.7.2. Buttons A.7.3. LEDs
A.8. Power x
A.8.1. Power Sequence A.8.2. Power Measurement A.8.3. Temperature Monitor
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.7.1. Switches

Table 6.  SW1 Pin Connections
SW1 Pin Board Label Function Default Settings
SW1.1 MSEL0 Mode select 0 for configuration OFF
SW1.2 MSEL1 Mode select 1 for configuration ON
SW1.3 MSEL2 Mode select 2 for configuration ON
Table 7.  SW2 Pin Connections
SW2 Pin Board Label Function Default Settings
SW2.1 USB MAX JTAG SEL
  • ON: UBII MAX® 10 JTAG select External JTAG header
  • OFF: UBII MAX® 10 JTAG select USB PHY
 OFF
SW2.2 SI5341 Enable
  • ON: Disables SI5341's outputs
  • OFF: Enables SI5341's outputs
 OFF
SW2.3 SI52202 Power Down
  • ON: Powers down SI52202
  • OFF: Powers up SI52202
 OFF
SW2.4 UART Enable
  • ON: Disables UART
  • OFF: Enables UART
 OFF
Table 8.  SW3 Pin Connections
SW3 Pin Board Label Function Default Settings
SW3.1 FPGA I2C Enable
  • ON: Isolates FPGA from main I2C chain
  • OFF: Connects FPGA to main I2C chain
 OFF
SW3.2 HPS I2C Enable
  • ON: Isolates HPS from main I2C chain
  • OFF: Connects HPS to main I2C chain
 OFF
SW3.3 Main PMBUS Enable
  • ON: Isolates the power module of VCC_core from main I2C chain.
  • OFF: Connects the power module of VCC_core to main I2C chain
 OFF
SW3.4 FPGA PMBUS Enable
  • ON: Isolates the power module of VCC_core from SDM PMBUS.
  • OFF: Connects the power module of VCC_core to SDM PMBUS
 OFF
Table 9.  SW4 Pin Connections
SW4 Pin Board Label Function Default Settings
SW4.1 JTAG Input Source
  • ON: Selects the PCIe* edge as JTAG master when the external JTAG is absent
  • OFF: Selects the onboard Intel® FPGA Download Cable as JTAG master when the external JTAG is absent
 OFF
SW4.2 Power MAX 10 Bypass ON: Bypasses the power MAX® 10 in the JTAG chain ON
SW4.3 Mictor Bypass
  • ON: Bypasses HPS in the JTAG chain
  • OFF: Enable HPS in the JTAG chain
 ON
SW4.4 FPGA Bypass
  • ON: Bypasses FPGA in the JTAG chain
  • OFF: Enables FPGA in the JTAG chain
 OFF
Table 10.  SW5 Pin Connections
SW5 Pin Board Label Function Default Settings
SW5 Power ON/OFF Powers on/off the board OFF
Table 11.  SW6 Pin Connections
SW6 Pin Board Label Function Default Settings
SW6.1 PCIe EP Present x16
  • ON: x16 select
  • OFF: x16 deselect
 ON
SW6.2 PCIe EP Present x8
  • ON: x8 select
  • OFF: x8 deselect
 OFF
SW6.3 PCIe EP Present x4
  • ON: x4 select
  • OFF: x4 deselect
 OFF
SW6.4 PCIe EP Present x1
  • ON: x1 select
  • OFF: x1 deselect
 OFF
Table 12.  SW7 Pin Connections
SW7 Pin Board Label Function Default Settings
SW7.1 SEL_A_B
  • ON: Selects SI52202 as clock source for PCIe* 4.0
  • OFF: Selects the PCIe* edge as clock source for PCIe* 4.0
 OFF
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