F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/02/2023

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Document Table of Contents

9.1.6. Registers

The auto-negotiation and link training registers are available per each Ethernet port the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP controls.

Refer to the F-tile Auto-Negotiation and Link Training Register Map to access register map and registers description. The register map documents the registers using the byte address offset. The physical Avalon Memory-Mapped Interface(AVMM) is based on 32-bit word addresses. However this document refers to the registers as byte addresses, you can convert to word addresses by shifting 2 bits to the right (divide by 4). You can use a byte enabled signal to address individual bytes.