F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/02/2023
Public

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9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface

Table 79.  PTP Peer-to-Peer (P2P) MeanPathDelay Reconfiguration InterfaceThe signals in this interface are clocked by the i_reconfig_clk clock and reset by the i_reconfig_reset signal of the PTP tile adapter. This clock and reset are used for all the reconfiguration interfaces in the IP core.
Port Name Width Description

i_reconfig_ptp_p2p_addr[16:0]

17 bits

Word address bus for PTP P2P MeanPathDelay and status registers.

i_reconfig_ptp_p2p_read

1 bit

Read request signal for PTP P2P MeanPathDelay and status registers.

i_reconfig_ptp_p2p_write

1 bit

Write request signal for PTP P2P MeanPathDelay and status registers.

i_reconfig_ptp_p2p_byteenable[3:0]

4 bits

Byte enable for PTP P2P MeanPathDelay read and write request signals.

o_reconfig_ptp_p2p_readdata[31:0]

32 bits

Read data from reads to PTP P2P MeanPathDelay and status registers.

o_reconfig_ptp_p2p_readdata_valid

1 bit

When set, read data from PTP P2P MeanPathDelay and status registers is valid.

i_reconfig_ptp_p2p_writedata[31:0]

32 bits

Write data for PTP P2P MeanPathDelay and status registers.

o_reconfig_ptp_p2p_waitrequest

1 bit

Avalon® memory-mapped interface stalling signal for operations on PTP P2P MeanPathDelay and status registers.