F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/02/2023
Public

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8.1. Ethernet Avalon® Memory-Mapped Interface Address Space

The Reconfiguration Ethernet interface (reconfig_eth) provides access to the Ethernet Hard IP Avalon® memory-mapped interface space for the local Ethernet Hard IP fracture, including MAC, PCS, and FEC interface, the interface to the PMA, as well as soft CSRs implemented in the FPGA fabric. All addresses are byte-based address even though the register description specifies 32 bit boundary.

Refer to the F-Tile Ethernet Hard IP Register Map to view the register map and registers description.

Table 65.  Reconfiguration Ethernet Avalon® Memory-Mapped Interface Address RangesThe description for the reconfiguration ethernet interface is provided in IP-XACT format upon IP core generation.
Register Type Address Range
F-Tile EMIB Configuration Registers 0x0000-0x00FC
Soft Control Status Registers (Soft CSRs) 0x0100-0x0FFC
EHIP Registers 0x1000-0x5FFC
FEC/Transceiver Interface Registers 0x6000-0x9FFC