F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/02/2023

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8. Configuration Registers

You access the Ethernet registers for the F-Tile Ethernet Intel® FPGA Hard IP using the Avalon® memory-mapped interface Ethernet reconfiguration interface on each channel. These registers use 32-bit addresses; for accessing individual bytes, use byteenable signals.

Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified result. Write operations to Reserved registers have an undefined effect. Accesses to registers that do not exist in your IP core variation, or to register bits that are not defined in your IP core variation, have an unspecified result. You should consider these registers and register bits Reserved. Although you can only access registers in 32-bit read and write operations, you should not attempt to write or ascribe meaning to values in undefined register bits.

For more information about specific reconfig_eth address register description, refer to the F-Tile Ethernet Intel® FPGA Hard IP Register Map and F-Tile Auto-Negotiation and Link Training Register Map IPXACT files.

Refer to Specifying the IP Core Parameters and Options for information about generating the .ipxact containing the register information.

Note: Unauthorized access to register sets outside of the configured Ethernet fractures is not recommended. For example, if your design is configured for 25G Ethernet, you should not be able to access additional variations such as 100G/400G.