F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/02/2023
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4.4.3. PTP Client Flow

You must implement proper TX and RX data flows prior to sending PTP commands to the IP core and utilizing the timestamps.
Attention: The following flows depict pseudo-code meant for conceptual, illustrative purposes. For definitive software routines, consult the design example.

The figures below depict the TX and RX client flows described in the PTP TX Client Flow and PTP RX Client Flow sections.

Figure 17. PTP TX Client Flow
The figure displays the following events in PTP TX client flow. For more information, refer to PTP TX Client Flow.
  • A: Reading TX raw offset data from IP
  • B: Calculating the TX offset value
  • C: Writing calculated TX offset value to the IP

Figure 18. PTP RX with RS-FEC Client Flow
The figure displays the following events in PTP RX with RS-FEC client flow. For more information, refer to PTP TX Client Flow
  • D: Reading RS-FEC cw_pos value from the IP
  • E: Calculating cw_pos adjustment value
  • F: Writing adjustment value to the IP
  • G: Reading RX raw offset data from IP
  • H: Calculating the RX offset value
  • I: Writing calculated RX offset value to the IP

Figure 19. PTP RX without RS-FEC Client Flow
The figure displays the following events in PTP RX with no RS-FEC client flow. For more information, refer to PTP RX Client Flow.
  • G: Reading RX raw offset data from IP
  • H: Calculating the RX offset value
  • I: Writing calculated RX offset value to the IP

Table 16.  Client Flow Glossary
Term Meaning
UI Unit interval. Indicates bit time of one serial bit for specific speed.

Unit interval is defined in 32-bit format, where bit [31:28] represent bit time in nanoseconds (ns) and bit [27:0] represent bit time in fractional nanoseconds (fns).

PL Total number of PMA physical lanes of the variant
FL Total number of FEC lanes of the variant
VL Total number of virtual lanes of the variant
apl Actual number of specific physical lane in a PMA quad. Possible values are 0, 1, 2, and 3.

For more information, refer to the Building Blocks chapter in the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.

pl Logical number corresponding to a specific physical lane. pl=0 typically refers to the top-most active physical lane.
fl Logical number of a specific FEC lane
vl Logical number of a specific virtual lane
read(reg_name) Performs CSR read from the reg_name register
write(reg_name, value) Performs CSR write with value to the reg_name register.
tx_pma_delay_ui Specifies TX serializer latency (in UI)
rx_pma_delay_ui Specifies RX deserializer latency (in UI)
tx_external_phy_delay Specifies TX external Ethernet PHY latency and board trace delay (in ns)
rx_external_phy_delay Specifies RX external Ethernet PHY latency and board trace delay (in ns)

UI Format

The UI format differs from the format of other variables. UI uses the {4-bit ns, 28-bit fractional ns} format. Other variables defined in the PTP TX/RX client flows use the {N-bit ns, 16-bit fns} format, where N is the largest number to store the calculation's max value.

If you use UI format in your calculation, you must convert the result to a 16-bit fractional nanoseconds (fns) format.