3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
The F-Tile Ethernet Intel® FPGA Hard IP parameter editor provides the parameters you can set to configure your F-Tile Ethernet Intel® FPGA Hard IP variation and simulation and hardware design examples.
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For information about the Example Design tab and Analog Parameters tab, refer to the F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide and Analog Parameters Options in F-Tile Architecture and PMA and FEC Direct PHY Intel FPGA IP User Guide.
Parameter |
Range |
Default Setting |
Parameter Description |
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General Options | |||
Advanced mode |
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Off |
When turned on, enables the Custom Ethernet line rate option and allows you to access the following FEC modes for 25GE-1.
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PMA type |
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FGT | PMA Channel Type.
Selects the F-Tile based targeted PMA type. Each PMA has a different data rate range and compliance specifications.
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FHT precoding enable |
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Disabled | Enables the FHT precoding. Available for PAM4 modes, always disabled for NRZ modes.
Note: This feature is used during the auto-negotiatiation and link training. When link training is disabled, the FHT precoding is enabled.
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Ethernet mode |
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10GE-1 | Ethernet Configuration. Specifies the overall port bandwidth across the number of physical lanes used by the port. Term XGE-Y represents:
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Custom Ethernet line rate | Varies based on the selected Ethernet mode. | 25.78125 Gbps | When turned on, this option allows you to choose the custom Ethernet line rate up to the maximum ethernet rate supported. This parameter is available when Advanced mode is enabled in the IP parameter editor. |
Client interface |
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MAC segmented | Selects data interface exposed to a client. Selected interface determines the Ethernet functional blocks enabled in the design.
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FEC mode |
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None | Selects the FEC mode for each port.
The IP core supports the following FEC types
For more information about FEC modes and the supported protocols, refer to the F-Tile Supported FEC Modes and Compliance Specifications table in the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide. |
PMA reference frequency |
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156.250000 | Selects the reference clock frequency used by the transceiver. 156.25 MHz is the recommended frequency for all Ethernet modes. This is the only supported frequency when using FHT or when auto-negotiation and link training (AN/LT) is enabled. 312.5 MHz is also supported when using FGT without AN/LT. 322.265625 MHz is supported when you select IEEE 802.3 BASE-R Firecode or RS(528,514), while using FGT without AN/LT. |
System PLL frequency |
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805.664062 | Selects the System PLL frequency. The core clock is equivalent to this frequency divided by 2.
Recommended frequency based on selected FEC mode:
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Custom system PLL Frequency | 805.6640625 - 903.125 MHz (with enabled PTP ) 322.265625 - 1GHz (with disabled PTP) |
N/A | If you choose the Custom option in the System PLL Frequency parameter, the IP core clock o_clk_pll is equivalent to half of the specified rate. |
External Custom Cadence Controller |
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Off | When turned on, enables the external custom cadence controller option and allows you to drive the i_custom_cadence port to DUT. You can use the parameter when sharing custom cadence controller with multiple IP instances. This parameter is available if you choose the Custom option in the System PLL Frequency parameter. |
Include Deterministic Latency Measurement |
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Off | When turned on, enables the built-in Deterministic Latency Measurement module within the IP.
This parameter is available if you choose the PCS66 FlexE option in the Client interface parameter.
Note: This parameter and Include Deterministic Latency Interface cannot be enabled at the same time.
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Include 32-bit soft CWBIN counters |
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Off | This parameter is available when FEC mode is enabled in the IP parameter editor. This soft logic converts the 8-bit CWBin0-3 registers in Hard IP (FEC block of F-Tile) to the 32-bit registers in Soft logic. |
Reconfig Clock Frequency | 100 to 250 MHz | 100 MHz | Avalon® memory-mapped interface reconfiguration clock. The interface uses this clock to access control status registers (CSRs). The clock supports 100 to 250 MHz frequency. |
Enable dedicated CDR Clock Output |
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Off | When turned on, enables the dedicated CDR clock output. When there is more than one channel number, the CDR clock output is connected to channel 0. This option is only applicable if the channel 0 is placed within FGT QUAD3 or UX FGT Quad2. |
MAC Options |
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Basic Tab |
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TX maximum frame size |
65 – 65535 | 1518 |
Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the TX statistics counters. In PCS Only, OTN, and FlexE variations, this parameter has no effect and remains at the default value of 1518. |
RX maximum frame size |
65 – 65535 | 1518 |
Maximum packet size (in bytes) the IP core can receive on the Ethernet link without reporting an oversized packet in the RX statistics counters. If you turn on Enforce Maximum Frame Size parameter, the IP core truncates incoming Ethernet packets that exceed this size. In PCS Only, OTN, and FlexE variations, this parameter has no effect and remains at the default value of 1518. |
Enforce maximum frame size |
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Off | Specifies whether the IP core is able to receive an oversized packet or truncates these packets. In a truncated packet, error signal indicates oversize and FCS error. |
Link fault generation option |
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Off | Specifies the IP core response to link fault events. Bidirectional link fault handling complies with the Ethernet specification, specifically IEEE 802.3 Figure 81-11. Unidirectional link fault handling implements IEEE 802.3 Clause 66: in response to local faults, the IP core transmits Remote Fault ordered sets in interpacket gaps but does not respond to incoming Remote Fault ordered sets. The OFF option is provided for backward compatibility. |
Bytes to remove from RX frames |
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Remove CRC bytes | Selects whether the RX MAC should remove CRC bytes, or remove CRC and PAD bytes, or do not remove anything from incoming RX frames before passing them to the RX MAC Client. If the PAD bytes and CRC are not needed downstream, this option can reduce the need for downstream packet processing logic |
Forward RX pause requests |
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O0ff | Selects whether the RX MAC forwards incoming PAUSE and PFC frames on the RX client interface, or drops them after internal processing.
Note: If flow control is turned off, the IP core forwards all incoming PAUSE and PFC frames directly to the RX client interface and performs no internal processing. In that case this parameter has no effect.
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Use source address insertion | - | - |
When enabled, the IP inserts source address in outgoing packets.
Note: Use Hexadecimal values to insert source address.
Source address insertion applies to PAUSE and PFC packets provided on the TX MAC client interface, but does not apply to PAUSE and PFC packets the IP core transmits in response to the assertion of i_tx_pause or i_tx_pfc[n] on the TX MAC client interface. |
TX VLAN detection |
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Off | Specifies whether the IP core TX statistics block treats TX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the TxFrameOctetsOK counter. If turned on, the IP core identifies these frames in TX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames. |
RX VLAN detection |
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Off | Specifies whether the IP core RX statistics block treats RX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frames in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the RxFrameOctetsOK counter . If turned on, the IP core identifies these frames in RX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames. |
Stop TX traffic when link partner sends PAUSE |
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No | When set to Yes, both SFC and PFC are supported. When a pause frame is received, the TX MAC stops sending traffic. When set to No, both SFC and PFC are supported. When a pause frame is received, the TX MAC does not stop sending traffic. When set to Disable, flow control is disabled entirely. |
Ready latency | 0 - 3 | 0 | Selects the ready Latency value on the TX client interface. readyLatency is an Avalon® ST interface property that defines the number of clock cycles of delay from when the IP core asserts the o_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon Interface Specifications. In MII PCS Only and MAC segmented variations, this parameter has no effect. Selecting a longer latency (higher number) eases timing closure at the expense of increased latency for the TX datapath in MAC+PCS variations. |
Enable TX Packing |
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Off | This parameter is available when Client interface is set to MAC segmented mode without PTP enabled for all rates ranging from 40G to 400G and with PTP enabled for all rates ranging from 50GE to 400GE When set to On, packing logic is inserted in TX direction. It removes idle segments in between the packets and maximizes throughput of the MAC. |
Enable asynchronous adapter clocks |
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Off | When turned on, you may drive the i_clk_rx and i_clk_tx clock signals different from o_clk_pll clock. Available only when Client interface is set to MAC Avalon® ST. |
PTP Tab |
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Enable IEEE 1588 PTP |
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Off | Enable this option to add IEEE 1588 PTP Timestamp offload functions to the IP core. The IP core can generate TX timestamps and RX timestamps. |
Timestamp accuracy mode |
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Advanced | Select PTP TX and RX timestamps accuracy mode. 12
In Basic mode, supports the following timestamps accuracy:
In Advanced mode, supports the following timestamps accuracy:
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Timestamp fingerprint width | 8 - 32 | 8 | Specify the width of the timestamp fingerprint in bits on the TX path. The default value is 8 bits. |
Specialized Tab |
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Enable strict preamble check |
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Off | If turned on, the IP core rejects RX packets whose preamble is not the standard Ethernet preamble (0x55_55_55_55_55_55). This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur. |
Enable strict SFD check |
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Off | If turned on, the IP core rejects RX packets whose SFD byte is not the standard Ethernet SFD (0xD5). This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur. |
Average inter-packet gap |
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12 | Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link. Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link. The default value of 12 complies with the Ethernet standard. The remaining values support increased throughput. The value of 1 specifies that the IP core transmits Ethernet packets as soon as the data is available, with the minimum possible gap. The IPG depends on the space you leave between frame data as you write it to the core. The IP core no longer complies with the Ethernet standard but the application has control over the average gap and maximizing the throughput. |
Enable preamble passthrough |
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Off | If turned on, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame. |
Additional IPG removed per AM period | 0-16536 | 0 | Specifies the number of inter-packet gaps the IP core removes per alignment marker period, in addition to the default number required for protocol compliance. Each increment of 1 in the value of Additional IPG removed per AM period increases throughput by 3ppm in 100GE variations. To specify larger throughput increases, use the Average Inter-packet Gap parameter. |
Auto-Negotiation and Link Training Options | |||
Enable auto-negotiation and link training |
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Off | Enables auto-negotiation and link training for the Ethernet port. You must instantiate the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP to support this feature. |
Configuration, Debug and Extension Options | |||
Enable Ethernet Debug Endpoint |
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Off | Enables the Ethernet debug endpoint. You must enable this parameter to allow the System Console access the Ethernet toolkit. |
Enable Native PHY Debug Endpoint |
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Off | Enables the Native PHY debug endpoint. You must enable this parameter to allow the System Console access the Transceiver toolkit. |