F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/02/2023
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7.10. FlexE and OTN Mode RX Interface

The F-Tile Ethernet Intel® FPGA Hard IP RX client interface in FlexE and OTN variations employs the PCS66 interface protocol.

The FlexE and 200GE/400GE OTN modes, the application allows to read 66b blocks from the RX PCS, bypassing the RX MAC.

The RX PCS acts as a source and the client acts as a sink in the receive direction.

Additionally, the OTN mode enables the collection of RX MAC statistics.

Table 54.  Signals of the PCS66 RX InterfaceAll interface signals are clocked by the RX clock. The signal names are standard Avalon-ST signals.

Name

Width

Description

o_rx_pcs66_d[1055:0]

o_rx_pcs66_d[527:0]

o_rx_pcs66_d[263:0]

o_rx_pcs66_d[131:0]

o_rx_pcs66_d[65:0]

1056 bits (400GE)

528 bits (200GE)

264 bits (100GE)

132 bits (40GE/50GE)

66 bits(10GE/25GE)

RX PCS 66b data for 1 block.

  • In FlexE mode, the RX PCS 66b data is aligned and descrambled but not decoded.
  • In OTN mode, the RX PCS 66b data is aligned and descrambled in 200GE/400GE.

o_rx_pcs66_valid

1 bit When asserted, indicates that the RX PCS 66b data is valid.

o_rx_pcs66_am_valid

1 bit Alignment marker indicator.

When asserted, Indicates the blocks on the RX PCS 66b data signal are identified as RS-FEC codeword markers.

Note:

This signal cannot be driven properly for 25GE with RS-FEC variant.

When the Deterministic latency Interface or Deterministic latency Measurement parameter is turned on, sync pulses are seen even for 25GE without RS-FEC variant and 10GE variant. When Deterministic latency Measurement parameter is turned on, the internal module handles this generation.

Figure 50. Receiving Data Using the PCS66 RX InterfaceThe figure shows how to read the 66b blocks directly from the RX PCS using the PCS mode RX Interface.

The 66b blocks follow Ethernet 64b/66b convention. The least significant 2 bits of each 66 block is a 2b sync header and the remaining 64b are data.

  • In FlexE mode, the data is aligned and descrambled..
  • In OTN mode, the data is aligned and descrambled in 200GE/400GE.

The data is only valid when o_rx_pcs66_valid is high. The contents of the o_rx_pcs66_d bus are not defined when o_rx_pcs66_valid is low.

The block order for the PCS66 mode RX interface is the same as the RX PCS interface. Blocks flow from LSB to MSB; the first block that the core receives is o_rx_pcs66_d[65:0].

The bit order for the PCS66 mode RX interface is the same as the RX PCS interface. Bits flow from least to most significant; the first bit that the core receives is o_rx_pcs66_d[0].

o_rx_pcs66_am_valid indicates the arrival of the alignment markers from the RX PCS. The alignment markers also depend on o_rx_pcs66_valid. When o_rx_pcs66_valid is low, o_rx_pcs66_am_valid is not valid.

  • In FlexE mode, when o_rx_pcs66_am_valid is high, o_rx_pcs66_d is undefined because the alignment markers do not get descrambled.
  • In OTN mode, when o_rx_pcs66_am_valid is high, o_rx_pcs66_d presents the received alignment markers.
Figure 51. Receiving Alignment Markers for FlexE Mode
Figure 52. Receiving Alignment Markers for OTN Mode