Visible to Intel only — GUID: GUID-193A9DEE-3CD1-4120-AC06-B6AAFB5F1674
Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs
Introduction To FPGA Design Concepts
Intel oneAPI FPGA Development
Getting Started with the Intel oneAPI DPC++/C++ Compiler for Intel FPGA Development
Defining a Kernel for FPGAs
Debugging and Verifying Your Design
Analyzing Your Design
Optimizing Your Kernel
Optimizing Your Host Application
Integrating Your Kernel into DSP Builder for Intel FPGAs
Integrating Your RTL IP Core Into a System
RTL IP Core Kernel Interfaces
Loops
Pipes
Data Types and Arithmetic Operations
Parallelism
Memories and Memory Operations
Libraries
Additional FPGA Acceleration Flow Considerations
Additional SYCL* HLS Flow Considerations
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs
Notices and Disclaimers
Set the Environment Variables and Launch Visual Studio* Code
Create an FPGA Visual Studio* Code Project
Enable Code Completion in a Visual Studio* Code Project
Configure Running and Debugging in a Visual Studio* Code Project
Debugging Your Kernel in Visual Studio* Code with a Native Debugger
Generate and View the FPGA Optimization Report
Build and Run the FPGA Hardware Image
Throughput
Resource Use
System-level Profiling Using the Intercept Layer for OpenCL™ Applications
Multi-Threaded Host Application
Utilizing Hardware Kernel Invocation Queue
Double Buffering Host Utilizing Kernel Invocation Queue
N-Way Buffering to Overlap Kernel Execution
Prepinning Memory
Simple Host-Device Streaming
Buffered Host-Device Streaming
Refactor the Loop-Carried Data Dependency
Relax Loop-Carried Dependency
Transfer Loop-Carried Dependency to Local Memory
Minimize the Memory Dependencies for Loop Pipelining
Unroll Loops
Fuse Loops to Reduce Overhead and Improve Performance
Optimize Loops With Loop Speculation
Remove Loop Bottlenecks
Improve fMAX/II with Shannonization
Optimize Inner Loop Throughput
Improve Loop Performance by Caching Data in On-Chip Memory
Global Memory Bandwidth Use Calculation
Manual Partition of Global Memory
Partitioning Buffers Across Different Memory Types (Heterogeneous Memory)
Partitioning Buffers Across Memory Channels of the Same Memory Type
Ignoring Dependencies Between Accessor Arguments
Contiguous Memory Accesses
Static Memory Coalescing
Specify Schedule fMAX Target for Kernels (-Xsclock=<clock target>)
Create a 2xclock Interface (-Xsuse-2xclock)
Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_name>)
Force Ring Interconnect for Global Memory (-Xsglobal-ring)
Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring)
Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder)
Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue)
Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking)
Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion)
Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion)
Pipeline Loops in Non-task Kernels (-Xsauto-pipeline)
Control Semantics of Floating-Point Operations (-fp-model=<value>)
Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>)
Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>)
Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>)
Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>)
Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
Allow Wide Memory Initialization (-Xsallow-wide-mif)
Visible to Intel only — GUID: GUID-193A9DEE-3CD1-4120-AC06-B6AAFB5F1674
Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
ATTENTION:
Only the SYCL* HLS flow supports this compiler option.
The Intel® oneAPI DPC++/C++ Compiler generates a ring-like wrapper structure to connect all register map interfaces for different kernels inside an RTL IP core. You can direct the compiler to generate different types of the wrapper by including the -Xsregister-map-wrapper-type=<default|high-fmax|low-latency> option in the icpx command, as shown in the following example:
Example
icpx -fsycl -fintelfpga –Xshardware -Xsregister-map-wrapper-type=<default|high-fmax|low-latency> source_file.cpp
Where:
- -Xsregister-map-wrapper-type=high-fmax: The ring wrapper contains pipeline stages to curtail it from being the fmax bottleneck of the IP core. The number of pipeline stages varies and depends on the number of kernels in the IP core.
- -Xsregister-map-wrapper-type=low-latency: The ring wrapper contains combinational logic only and does not introduce extra latency for the Avalon® Memory-Mapped signals between the IP core boundary and the kernel.
- -Xsregister-map-wrapper-type=default: When you set it to default or omit this compiler option, the compiler automatically infers the ring wrapper type. This compiler option does not change the signals on the register map interfaces in any manner.
CAUTION:
- If you attempt to use this option in the full-system flow, the compiler issues a warning and ignores the option. The compiler still generates the ring wrapper, but the wrapper type used in the full-system flow may differ from the default wrapper type used in the SYCL* HLS flow.
- If any kernel in the IP core contains streaming invocation interfaces and register map kernel arguments, and you specify the high-fmax version of the register map wrapper, the compiler returns an error message indicating this combination is not supported.
Parent topic: Optimization Flags