Developer Guide

Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs

ID 785441
Date 5/08/2024
Public

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Document Table of Contents

Generate Register Map Wrapper (-Xsregister-map-wrapper-type)

ATTENTION:
Only the SYCL* HLS flow supports this compiler option.

The Intel® oneAPI DPC++/C++ Compiler generates a ring-like wrapper structure to connect all register map interfaces for different kernels inside an RTL IP core. You can direct the compiler to generate different types of the wrapper by including the -Xsregister-map-wrapper-type=<default|high-fmax|low-latency> option in the icpx command, as shown in the following example:

Example

icpx -fsycl -fintelfpga –Xshardware -Xsregister-map-wrapper-type=<default|high-fmax|low-latency> source_file.cpp

Where:

  • -Xsregister-map-wrapper-type=high-fmax: The ring wrapper contains pipeline stages to curtail it from being the fmax bottleneck of the IP core. The number of pipeline stages varies and depends on the number of kernels in the IP core.
  • -Xsregister-map-wrapper-type=low-latency: The ring wrapper contains combinational logic only and does not introduce extra latency for the Avalon® Memory-Mapped signals between the IP core boundary and the kernel.
  • -Xsregister-map-wrapper-type=default: When you set it to default or omit this compiler option, the compiler automatically infers the ring wrapper type. This compiler option does not change the signals on the register map interfaces in any manner.
CAUTION:
  • If you attempt to use this option in the full-system flow, the compiler issues a warning and ignores the option. The compiler still generates the ring wrapper, but the wrapper type used in the full-system flow may differ from the default wrapper type used in the SYCL* HLS flow.
  • If any kernel in the IP core contains streaming invocation interfaces and register map kernel arguments, and you specify the high-fmax version of the register map wrapper, the compiler returns an error message indicating this combination is not supported.