Design Guide: Hybrid PCB stack-up helps improve signal integrity performance for high-speed signaling at lower cost than an all low loss stack-up.
Design Guide: Describes how a hybrid PCB stack-up helps improve signal integrity performance for high-speed signaling at lower cost than an all low loss stack-up.
Erasure coding extends Swift* storage capabilities to improve data availability through parity, reducing cost and storage requirements.
Storage policies, such as the Intel® Intelligent Storage Acceleration Library, and erasure coding extend Swift* storage capabilities to improve data availability through parity for half the storage requirements and less cost than triple replication.Full View >
White Paper: Intel® Xeon® and Intel® Itanium® processor-based servers scale effective computing capabilities and lower power and cooling costs.
Discusses strategy to scale effective computing capabilities while containing power and cooling costs with Intel® Xeon® and Intel® Itanium® processor-based servers, delivering massive performance increases, cost savings and energy efficiency.
Spec Update: Device and documentation errata, specification clarifications and changes for the Intel® Xeon® processor 5400 series.
Document outlines thermal and mechanical operating limits and specifications as well as reference thermal solutions for the Intel® X79 Express Chipset Platform Controller Hub.
White Paper: Intel® Xeon™ processor family powered by the Intel® NetBurst™ microarchitecture with Hyper-Threading Technology.
Enabling applications to support more features, increase throughput and response times, and serve more concurrent users, the Intel® Xeon™ processor family delivers highly scalable performance powered by the Intel® NetBurst™ microarchitecture.
Thermal and Mechanical Design Guide: Intel® 5000 Series Chipset Memory Controller Hub.
Discusses packaging technology, thermal specification, metrology, and solution for the Intel® 5000 series Chipset Memory Controller Hub.