Cyclone® 10 LP FPGA
The Cyclone® 10 LP FPGA extends the Cyclone FPGA series leadership in low-power devices targeted for high-volume and cost-sensitive applications.
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Ideal for High-Volume and Cost-Sensitive Applications
Benefits
Half the Power at Half the Cost1
Ideal for high-volume, cost-sensitive functions, the Cyclone 10 LP FPGA is designed for a broad spectrum and suits smart and connected end applications across many market segments.
Lower Your System Costs
All Cyclone 10 LP FPGAs require only two core power supplies for operation, simplifying your power distribution network and saving you board costs, board space, and design time. This enables you to design a lower cost system.
Reduce Power Consumption
Built on a power-optimized 60 nm process, the Cyclone 10 LP FPGA extends the low-power leadership of the previous-generation Cyclone V FPGA. The latest generation devices reduce core static power by up to 50 percent compared with the previous generations.
Applications
Embedded Systems
The increasing performance requirements of today's embedded systems is driving microprocessor selection. Cyclone 10 LP FPGAs are ideally suited for these applications. With a range of intellectual property (IP) blocks, such as I2C, serial peripheral interface (SPI), UART, parallel I/O blocks, and packages supporting over 500 I/Os, designers can scale to fit the application needs.
Chip-to-Chip Interfacing
Cyclone 10 LP FPGAs are an ideal solution for interfacing between application specific standard products (ASSPs). These devices allow designers to combine the interfacing with image pipeline processing for real-time applications that need high frame rates, low latency, and high-processing throughput.
Motor Control
These FPGAs provide flexibility for general-purpose interfacing with a maximum I/O count of up to 525 user I/Os while supporting the customer’s diverse drive needs. These devices support a wide variety of industrial Ethernet protocols and are leveraged to implement pulse width modulator (PWM) and encoder interfaces, which when repeated multiple times in parallel, allows for multi-axis control.
Key Features
Embedded Multipliers
Each embedded multiplier block in the devices supports one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers. Cascade multiplier blocks to form wider or deeper logic structures.
Logic Elements and Logic Array Blocks
The logic array block (LAB) consists of 16 logic elements (LEs), each with four inputs, a four-input look-up table (LUT), a register, and output logic. The four-input LUT is a function generator that can implement any function with four variables.
Embedded Memory Blocks
The embedded memory structure consists of M9K memory blocks columns. Each M9K memory block of on the device provides 9 Kb of on-chip memory.
Single Event Upset (SEU)
The cyclic redundancy check (CRC) error detection feature can check for an SEU continuously, automatically confirming the accuracy of the configuration data stored in the device and alerting the system to an occurrence of a configuration error.
Additional Resources
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Development Boards
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Intellectual Property
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FPGA Design Software
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Where to Buy
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Product and Performance Information
Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.